`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/11 10:03:27
// Design Name: 
// Module Name: fsm_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module fsm_test(
    input clk,
    input reset,
	input x,
    output reg  z
);

    // FSM state declaration
    reg [2:0] current_state, next_state;
    parameter 	IDLE = 3'b000,
              	A = 3'b001,
              	B = 3'b010,
				C = 3'b011,
              	D = 3'b100,
				E = 3'b101,
				F = 3'b110,
              	G = 3'b111;

    // State register
    always @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            IDLE: next_state = x ? A : IDLE;
            A: next_state = x ? A : B;
            B: next_state = x ? F : C;
            C: next_state = x ? D : G;
			D: next_state = x ? A : E;
			E: next_state = x ? C : A;
			F: next_state = x ? A : B;
			G: next_state = x ? F : G;
        endcase
    end

always @(posedge clk or posedge reset) begin
      if (reset)begin
            z <=1'b0;
			end

		else begin
        z <= (current_state == E);
        end
end

    // // Output logic
	// always @(posedge clk or posedge reset) begin

 	// //always @(*) begin
    //   if (reset)begin
    //         z <=1'b0;
	// 		end
    //     else if(current_state== E)
	// 		   z <=1'b1;
    //     else 
    //          z <=1'b0; 

	// end



	/*assign C[1] = (current_state == S1);
    assign C[2] = (current_state == S2 || current_state == S4);
    assign C[3] = (current_state == S3);
	assign C[4] = (current_state == S5);
    assign lights_c[2] = (current_state == S0||current_state == S1||current_state == S5);
    assign lights_c[1] = (current_state == S2);
    assign lights_c[0] = (current_state == S2 || current_state == S3);
    assign lights_p[2] = (current_state == S3);
    assign lights_p[1] = (current_state == S4);
    assign lights_p[0] = (current_state == S0||current_state == S1||current_state == S2||current_state == S5);
	*/
	

endmodule

